INEL 4215

Computer Architecture and Organization

RISC vs. CISC

RISC – Reduced Instruction Set Computer

CISC – Complex Instruction Set Computer

CISC Design

- Design an ISA emphasizing doing more with each instruction

- Wide variety of addressing modes

- Complex instructions

- Instruction lengths may vary

- Time to execute instructions vary

Why CISC

- More operations into a program size

- Cost of memory – historical

- Assembly closer to high level languages.

- Narrow this gap.

As manufacturers added more instructions, higher clock speeds were not supported.

CISC did not support prefetching, pipelining, and superscalar.

RISC came along

- Reduced number of instructions

- Minimum complexity of instructions.

- Exploit caching, pipelining, and superscalar.

- One instruction per cycle. (single clock cycle – goal) (pipelining).

- Fixed instruction length

1 word – specifies everything needed: operation, operands, results, where to place results, which one is next instruction

- Only load and store instructions can access memory

Operands in registers

Minimizes traffic between processor and memory.

Minimizes pipeline delays.

- Simplified addressing modes.

Two addressing modes.

Register indirect – register contains address of operands

Indexed – address operand is R[register] + constant

- Fewer Simpler Operations

Shorter clock cycles.

Complex instructions – decomposed into simpler instructions.

Cache – keep up with execution

- Delayed Loads and Branches

If load, store, branch require more than one clock cycle, then another instruction not dependent on the result may be issued.

Compiler will aid with this.

- Prefetch and speculative execution

Speculative execution -> When branch occurs. Execution on target address begins not knowing if the condition was met. If not results is discarded.

- Let the compiler do it

Out of order execution

Compiler will optimize.

Example: PowerPC - RICS architecture.