Gladys Omayra Ducoudray


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EXAM1

Courses > INEL 4205

Fecha

Clase

Seccion

Tema

Problemas

17-Ago

1

1

Binary Systems.
Digital Systems. Binary Numbers.

 

19-Ago

2

1

Number Base Conversions. Octal and Hexadecimal Numbers. Complements. Signed Binary Numbers. Binary Codes. Binary Storage and Registers. Binary Logic.

 

22-26 Ago

 


2

Boolean Algebra and Logic Gates.
Basic Definitions. Axiomatic Definition of Boolean Algebra. Basic Theorems and Properties of Boolean Algebra. Boolean Functions. Canonical and Standard Forms. Other Logic Operations. Digital Logic Gates. Integrated Circuits.

 

29- 2Ago

 

3

Gate-Level Minimization.
The Map Method. Four-Variable Map. Five-Variable Map. Product of Sums Simplification. Don't-Care Conditions. NAND and NOR Implementation. Other Two-Level Implementations. Exclusive-OR Function. HardwareDescriptionLanguage(HDL).

PRESENTACION DE CLASE

   

4

Combinational Logic.
Combinational Circuits. Analysis Procedure. Design Procedure. Binary Adder-Subtractor. Decimal Adder. Binary Multiplier. Magnitude Comparator. Decoders. Encoders. Multiplexers. HDLFor CombinationalCircuits.

Presentacion de Clase

   

5

Synchronous Sequential Logic.
Sequential Circuits. Latches. Flip-Flops. Analysis of Clocked Sequential Circuits. HDL For Sequential Circuits. State Reduction and Assignment. Design Procedure.

 
   

6

Registers ad Counters.
Registers. Shift Registers. Ripple Counters. Synchronous Counters. Other Counters. HDL for Registers and Counters.

 
   

7

Memory and Programmable Logic.
Introduction. Random-Access Memory. Memory Decoding. Error Detection and Correction. Read-Only Memory. Programmable Logic Array. Programmable Array Logic. Sequential Programmable Devices.

 
   

8

Register Transfer Level.
Register Transfer Level (RTL) Notation. Register Transfer Level in HDL. Algorithmic State Machines (ASM). Design Example. HDL Description of Design Example. Binary Multiplier. Control Logic. HDL Description of Binary Multiplier. Design With Multiplexers.

 
   

9

Asynchronous Sequential Logic.
Introduction. Analysis Procedure. Circuits With Latches. Design Procedure. Reduction of State and Flow Tables. Race-Free State Assignment. Hazards. Design Example.



 
   

10

Digital Integrated Circuits.
Introduction. Special Characteristics. Bipolar-Transistor Characteristics. RTL and DTL Circuits. Transistor-Transistor Logic (TTL). Emitter-Coupled Logic (ECL). Metal-Oxide Semiconductor (MOS). Complementary MOS (CMUS). CMOS Transmission Gate Circuits. Switch-Lever Modeling With HDL.

 
   

11

Laboratory Experiments.
Introduction to Experiments. Binary and Decimal Numbers. Digital Logic Gates. Simplification of Boolean Functions. Combinational Circuits. Code Converters. Design with Multiplexers. Adders and Subtractors. Flip-flops. Sequential Circuits. Counters. Shift Registers. Serial Addition. Memory Unit. Lamp Handball. Clock-Pulse Generator. Parallel Adder and Accumulator. Binary Multiplier. Asynchronous Sequential Circuits. Verilog HDL Simulation Experiments.

 
   

12

Standard Graphic Symbols.
Rectangular-Shape Symbols. Qualifying Symbols. Dependency Notation. Symbols For Combinational Elements. Symbols For Flip-Flops. Symbols For Registers. Symbols For Counters. Symbol For RAM.

 

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